The ongoing development of semiconductor memory technology is driving memory devices to higher level of integration, lower power consumption, and faster speed. Compared to dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices do not need to periodically refresh the memory cells to maintain the data stored therein. Therefore, SRAM devices have been widely used in many applications.
Recently, fin-type transistors, such as fin field effect transistors (finFETs), have been used to replace planar transistors in logic devices. Embedded static random access memory (SRAM) devices have been widely used, SRAM bit cells have thus, been designed using FinFETs. In a FinFET bit cell, the channel has raised, fin-like structure, allowing the gate to be placed on two or more sides of the channel to improve conduction and leakage control. As the fin width is constant, it is not convenient to use the width of the active area to define the finFET SRAM ratio as is the case in conventional planar SRAM devices.
When the SRAM bit cells are formed using finFETs, the effective width is constant, the SRAM ratio may only be adjusted by changing the critical dimension (CD). However, when compared with planar SRAM devices, finFET RAM devices may have a smaller process window. It is thus challenging to widen the process window for finFET formed SRAM devices.